Analysis of the aliasing effect caused in hardware-in-the-loop when reading PWM inputs of power converters

Hardware-in-the-loop (HIL) systems are commonly used to debug controllers in closed-loop operation. Therefore, the frequency response of the emulated subsystem is of special relevance. Undesirable oscillations can appear as a consequence of digitally sampling the switch control signals in power converter HIL models. These oscillations at relatively low frequencies, below the switching frequency, may confound the closed-loop operation and, therefore, the appropriate debugging of the controller. This paper shows that the lost information when an HIL model reads a PWM signal may create some output offset error or steady-state fluctuations, especially when the switching period and the sampling step get closer. The aliasing frequencies produced by the input sampling are calculated, and the small-signal analysis explains the relation between the output oscillation and the input PWM sub-harmonics. The output error spectrum proves that the main error sub-harmonics have the same aliasing frequency components. Both captured oscilloscope results obtained by an NI myRIO device and MATLAB simulations verify that significant distortions can be seen in the output inductor current if there is a low aliasing frequency in the digital version of the input PWM signal read by the HIL mode

Comparison of different design alternatives for hardware-in-the-loop of power converters

This paper aims to compare different design alternatives of hardware-in-the-loop (HIL) for emulating power converters in Field Programmable Gate Arrays (FPGAs). It proposes various numerical formats (fixed and floating-point) and different approaches (pure VHSIC Hardware Description Language (VHDL), Intellectual Properties (IPs), automated MATLAB HDL code, and High-Level Synthesis (HLS)) to design power converters. Although the proposed models are simple power electronics HIL systems, the idea can be extended to any HIL system. This study compares the design effort of different coding methods and numerical formats considering possible synthesis tools (Precision and Vivado), and it comprises an analytical discussion in terms of area and speed. The different models are synthesized as ad-hoc modules in general-purpose FPGAs, but also using the NI myRIO device as an example of a commercial tool capable of implementing HIL models. The comparison confirms that the optimum design alternative must be chosen based on the application (complexity, frequency, etc.) and designers’ constraints, such as available area, coding expertise, and design effor

Sub-harmonic oscillations attenuation in hardware-in-the-loop models using the Integration Oversampling Method

Hardware-in-the-loop (HIL) technology has become widespread for testing purposes, gaining special importance in micro-grids and renewable energy. One of the main challenges in HIL technology is its use in mid or high-frequency applications. In those cases, oversampling gate signals is a must to obtain enough accuracy and avoid undesirable sub-harmonic oscillations in the emulation that would not appear in a real scenario or offline electrical simulation. However, handling the extra information obtained through oversampling increases significantly the complexity of switched models since the oversampling methods deal with more than one sample per simulation step. It leads to extra design effort if the models are designed ad-hoc or increased hardware resources when using vendor tools that implement oversampling techniques. In both cases, oversampling traditionally implies an increase in the overall cost of the HIL system. This paper proposes the Integration Oversampling Method (IOM), which manages the extra information obtained through oversampling with a minimum impact on the models’ complexity. In fact, the power model is not changed at all and uses just one switch state per simulation step. The method consists in adding a small hardware block in the input of the gate signals. Using the additional information obtained through oversampling, it generates a set of switch states in every simulation step that minimizes the integrated error in the input reading. The experimental results obtained through an NI myRIO device show clearly enhanced performance when using IOM both in transient and steady-state operation. At the same time, the additional hardware resources necessary for IOM implementation are negligibl

Mejoras en la precisión de Hardware in the Loop aplicado a convertidores conmutados: alternativas de diseño y atenuación de oscilaciones por aliasing

Tesis Doctoral inédita leída en la Universidad Autónoma de Madrid, Escuela Politécnica Superior, Departamento de Tecnología Electrónica y de las Comunicaciones. Fecha de Lectura: 24-11-202

Comparison of power converter models with losses for hardware-in-the-loop using different numerical formats

Nowadays, the Hardware-In-the-Loop (HIL) technique is widely used to test different power electronic converters. These real-time simulations require processing large data at high speed, which makes this application very suitable for FPGAs (Field Programmable Gate Array) as they are capable of parallel processing. This paper provides an analytical discussion on three HIL models for a full-bridge converter. The three models use different possible numerical formats, namely float and fixed-point, the latter with and without optimizing the width of signals to the embedded DSP (Digital Signal Processors) blocks of the FPGA. The optimized fixed-point model (OFPM) uses three and two times fewer DSP blocks or LUTs (Look Up Tables), and the maximum achievable clock frequency is also up to 35 % and 25 % higher than the float model and non-optimized fixed-point model (nOFPM), respectively. Furthermore, the models’ accuracy is proportional to the clock frequency, thus the OFPM is also the most accurate model. Finally, the paper shows the differences in the simulation when the models include or not losses, proving that not including losses leads to high errors, especially during transientsThis research was funded by Spanish Ministerio de Economía y Competitividad grant number TEC2013-43017-